1. Field of the Invention
The present invention relates to a digital-to-analog (D/A) converter circuit for converting digital signals to analog signals, a drive circuit for a display, and a display that makes use of the drive circuit.
2. Description of Related Art
With its thin, light and low-power consumption characteristics, liquid crystal displays (LCDs) are widely employed for office automation, customer use, industrial use and the like, as a flat panel display essential in the age of info-communication. Generally, such a liquid crystal display is provided with a liquid crystal drive circuit (liquid crystal drive IC) which includes a gradation voltage generator, a decoder circuit, an amplifier and the like. The gradation voltage generation circuit generates multiple gradation voltages. The decoder circuit selects a corresponding gradation voltage from the multiple gradation voltages according to the inputted image data. The amplifier performs current amplification on the gradation voltage selected by the decoder circuit, which is then supplied to the liquid crystal panel via source wirings.
FIG. 22 is a block diagram showing a configuration of a source-side liquid crystal drive circuit 1 of a conventional 8 bit type. As shown in FIG. 22, the source-side liquid crystal drive circuit 1 includes a receiver and serial/parallel conversion circuit 2, a shift register circuit 3, a latch circuit 4, a gradation voltage generation circuit 5, a decoder circuit 6, an amplifier 7 and the like. The receiver and serial/parallel conversion circuit 2 receives serial image data transmitted from a timing controller (not shown), and converts the image data into parallel pixel-by-pixel gradation data D00 to D07. The shift register circuit 3 generates, in accordance with clock signals inputted thereto, data capture signals to be used in the latch circuit 4, and outputs the signals to the latch circuit 4.
According to the data capture signals inputted from the shift register circuit 3, the latch circuit 4 retains digital gradation data corresponding to the number of outputs. The gradation voltage generation circuit 5 generates gradation voltages VDATA0 to VDATA255 and inputs the voltages to the decoder circuit 6. From among the inputted gradation voltages VDATA0 to VDATA255, the decoder circuit 6 selects, for each output, a gradation voltage corresponding to the gradation data D00 to D07 transmitted from the latch circuit 4. Note that in the decoder circuit 6, the gradation voltages VDATA0 to VDATA255 are shared among outputs of the same polarity.
Thereafter, each of the gradation voltages selected by the decoder circuit 6 is, for example, outputted to input terminals t1 to t720 of amplifiers 7 respectively provided for each output, in a case where the number of outputs is 720. When the gradation voltages are selected by the decoder circuit 6, all of the outputs of the amplifiers 7 charge and discharge source wirings (out1 to out720), and supply the selected voltages, via the source wirings, to corresponding pixels on the liquid crystal display panel.
FIG. 23 shows a configuration of a conventional decoder circuit 6. As shown in FIG. 23, the decoder circuit 6 includes 720 decoder unit circuits 61 corresponding to the number of outputs. The gradation voltages VDATA0 to VDATA255 are shared among the 720 decoder unit circuits 61. Each decoder unit circuit 61 may be configured of 8 switch devices 62 in series to which pieces of gradation data D00 to D07 are respectively inputted in control units. Gradation voltages VDATA0 to VDATA255 are respectively supplied to first ends of the 8 switch devices 62 in series, and second ends thereof are collectively connected to an input terminal of the amplifier 7. These switch devices 62 are controlled to be turned on/off according to the gradation data VDATA0 to VDATA255 transmitted from the latch circuit 5. Then, among the gradation voltages VDATA0 to VDATA255, the gradation voltages in which all 8 of the switch devices 62 are turned on are outputted to each of the input terminals t1 to t720 of the amplifiers 7. Note that the decoder circuit 6 may be configured otherwise.
In recent years, there is an increasing demand for displaying a larger number of colors on liquid crystal displays used for TV sets. Accordingly, the need for multi-bit liquid crystal drive circuits is enlarging year by year, and a 10-bit or 12-bit liquid crystal drive circuit has become the mainstream. However, in the aforementioned decoder circuit 6, a doubled number of switch devices 62 is required for every extra bit, and the circuit area is also doubled. Since the decoder circuit 6 part mainly accounts for the chip area of a liquid crystal drive circuit, an increase in the number of bits enlarges the chip area of a liquid crystal drive circuit to a great extent. A 10-bit liquid crystal drive circuit, for example, requires a chip area four times larger than that of an 8-bit liquid crystal drive circuit. As for a 12-bit liquid crystal drive circuit, a chip area of 16 times the area of the 8-bit liquid crystal drive circuit is required. For this reason, the cost for a liquid crystal drive circuit rises, while the implementation possibility is lowered. Similarly, the required number of wirings for gradation voltages (gradation lines) is doubled for every extra bit, excessively increasing the amount of wirings in the case of multiple bits. This increase in the amount of wirings influences the chip area.
Hence, implementation of a multi-bit liquid crystal drive circuit is difficult with merely a simple gradation voltage generation circuit 5 and a decoder circuit 6. In this regard, a conventional technique of reducing the area and number of gradation lines of the decoder circuit 6 is proposed (Patent Document 1). FIG. 24 shows a conventional D/A conversion circuit 10 described in Patent Document 1. The D/A conversion circuit 10 shown in FIG. 24 is an example of a 6-bit liquid crystal drive circuit. The D/A conversion circuit 10 is provided with a ladder resistor circuit 11 that generates voltages V1 to V17, a decoder circuit 12, an amplifier 13, and a capacitor voltage dividing circuit 14 including capacitors C1, C2 and C3. The capacity ratio among the capacitors C1, C2 and C3 is set to be 1:2:1.
Here, an explanation will be given for an operation of the conventional D/A conversion circuit 10 described in Japanese Patent Application Laid-open Publication No. Hei 11-109928.
Firstly, the decoder circuit 12 selects, from voltages V1 to V17 generated by the ladder resistor circuit 11, two adjacent voltages corresponding to most significant four bits of the gradation data. For example, if the gradation data of the most significant four bits is 0000, V1 and V2 are selected. Meanwhile, if the gradation data of the most significant four bits is 1111, V16 and V17 are selected. Then, D/A conversion is carried out by dividing the difference between the two selected voltages through changing the connection state of the capacitors C1, C2 and C3 in accordance with least significant two bits of the gradation data. The amplifier 13 performs current amplification on the thus divided voltage, which is then supplied to source wirings. Hence, the D/A conversion circuit 10 is configured such that D/A conversion is performed on the gradation data of the least significant two bits with the capacitors C1, C2 and C3 of the capacitor voltage dividing circuit 14, while D/A conversion is performed on the gradation data of the most significant four bits with the ladder resistor circuit 11 and the decoder circuit 12.
By employing the above configuration, the chip area of a liquid crystal drive circuit can be made smaller because the decoder circuit 12 and the number of gradation lines can be reduced for the least significant two bits. For example, in a case of applying the conventional technique to an 8-bit liquid crystal drive circuit, the area of the decoder circuit is as large as 6 bits and the required number of gradation lines is 64. Meanwhile, in the case of a 10-bit liquid crystal drive circuit, the area of the decoder circuit is as large as 8 bits and the required number of gradation lines is 256.
However, the conventional D/A conversion circuit 10 has the following drawback. That is to say, the conventional D/A converter 10 requires three or more capacitors for the configuration of the capacitor voltage dividing circuit 14, and the capacitor values need to be in a ratio relationship. As it is difficult to achieve an ideal capacity ratio for all of the output pins, voltages vary among the output pins. In addition, since offset voltages differ among the outputs of the amplifiers 13, further variance occur among the outputted voltages. Moreover, since three or more capacitors are needed, complicated switching of the capacitors is required, which necessitates a large number of switch devices. For this reason, caused is a problem of deviation in the outputted voltages due to feed through of the switch devices (charge splitting effect). As has been described, the conventional D/A conversion circuit 10 tends to be influenced by production variation, which inhibits the fabrication of a high-precision D/A conversion circuit.
Furthermore, since D/A conversion by use of capacitors is performed only on the gradation data of least significant two bits, the area of the decoder circuit and number of gradation lines are increased along with an increase in the number of bits. Accordingly, the area of a chip cannot be reduced to a large extent. For example, in a case of a 12-bit liquid crystal drive circuit, the area of the decoder circuit is as large as 10 bits and 1024 gradation lines are required. In a case of a 14-bit liquid crystal drive circuit, the area of the decoder circuit is as large as 12 bits and as much as 4096 gradation lines are required. Thus, even by applying the conventional technique, the area of the multi-bit liquid crystal drive circuit cannot be reduced to a large extent, leading to a rise in the cost of the liquid crystal drive circuit.
The area of the decoder circuit can otherwise be reduced by increasing the number of least significant bits on which D/A conversion is performed by the capacitor voltage driving circuit 14, to three bits or four bits. In this case, however, the number of capacitors in the capacitor voltage driving circuit 14 needs to be increased, which does not reduce the chip area after all. Consequently, the problem of conversion precision due to production variation becomes prominent.